U.S. Pat. No. 5,778,431 discloses a data processing circuit with a dynamically detachable device. A part of the memory space of the data processing circuit is associated with the detachable device. The data processing circuit has a cache memory. When the detachable device is detached during operation, a problem can arise when data corresponding to the addresses for the detachable device is stored in the cache memory. After detachment, write back from the cache memory is no longer possible, so that inconsistencies can arise. Therefore special measures are needed in relation to caching of data from such a detachable device.
One way to circumvent this problem is to avoid all caching data for addresses associated with the detachable device, but this reduces system performance. U.S. Pat. No. 5,778,431 discloses a solution that involves automatic write back of cache lines that contain data for addresses in the detachable device. Two registers are provided, containing data that indicates a start address and an end address of said part of the memory space respectively. Two comparators compare address tags of cached data with the data in the registers. On detachment of the device the address tags of all cache lines are compared with the start and end address and cache lines that are found to have address tags between start and end address are invalidated.
However, it has been found that this leads to excessive invalidation of data.